1. Field of the Invention
The present invention relates to a semiconductor sensor, and more particularly to a semiconductor sensor for detecting an external force such as a pressure, an acceleration, or the like.
2. Description of the Relevant Art
It is known in the art from Japanese laid open patent publication No. 53-153537, for example, that when a stress is applied to a field-effect transistor made of a piezoelectric semiconductor such as GaAs, the drain current of the field-effect transistor varies.
The applicant has previously proposed a cantilever-type semiconductor sensor based on the above nature of a field-effect transistor, as disclosed in Japanese laid-open patent publication No. 2-194343.
FIG. 1 of the accompanying drawings shows, in perspective, the external physical structure of the proposed cantilever-type semiconductor sensor. FIG. 2 of the accompanying drawings shows the circuit arrangement of the proposed semiconductor sensor.
As shown in FIG. 1, the cantilever-type semiconductor sensor, generally designated by the reference numeral 101, comprises a semiconductor substrate 102 and a crystalline layer 103 deposited on the semiconductor substrate 102 by way of epitaxial growth. The crystalline layer 103 includes an FET (field-effect transistor) 104. The semiconductor substrate 102 includes a flexible region 105 of reduced thickness defined by a recess in the surface thereof remote from the crystalline layer 103.
The semiconductor substrate 102 includes a fixed region 106 on one side of the flexible region 105 and a weight region 108 on the other side of the flexible region 105. The flexible region 105 has an end 107 adjacent to the fixed region 105 and an end 110 adjacent to the weight region 108.
The electric circuit of the semiconductor sensor 101 includes the FET 104 for detecting a stress developed by an external force that is applied to the weight region 108 at its center of gravity 109, a current-to-voltage (I-V) converter 3 for generating a voltage output corresponding to a drain current ID from the FET 104, a pair of resistors R1, R2 for applying a gate bias voltage VG to the gate G of the FET 104, and a power supply VDD.
The FET 104 has a drain D connected to the power supply VDD. The gate bias voltage VG, which is produced by dividing the voltage from the power supply VDD with the resistors R1, R2, is applied to the gate G of the FET 104.
The current-to-voltage converter 3 comprises an operational amplifier 3a and a feedback resistor 3b. The FET 104 has a source S connected to an inverting input terminal 3c of the operational amplifier 3a. The operational amplifier 3a has a noninverting input terminal 3d grounded. The FET 104 is driven at a constant voltage with the potential difference between the input terminals 3c, 3d of the current-to-voltage converter 3 being substantially zero.
When a stress is applied to the FET 104, the drain current ID of the FET 104 varies, and the variation in the drain current ID is detected and outputted as a voltage output 3e by the current-to-voltage converter 3.
It has been confirmed by a simulation process that a strain or deformation which occurs in the crystalline layer 103 when an external force is applied perpendicularly to the weight region 108 is maximum at the end 107 of the flexible region 105, and is almost zero at the end 110 thereof.
Therefore, the FET 104, which is in the form of a single unit and has a small area, is positioned on the end 107 of the flexible region 105, as shown in FIG. 1, in order to maximize the variation in the drain current ID of the FET 104 thus positioned, i.e., the sensitivity of the semiconductor sensor 101, at the time an external force is imposed on the semiconductor sensor 101.
However, the FET 104 of the type described above is problematic in that the drain current ID suffers irregular fluctuations (noise) even when no stress is applied to the semiconductor sensor 101, and hence no sufficient signal-to-noise ratio is provided in a range of small stresses applied.